|
With the emergence of important climate saving legislation such as 80 PLUS, Climate Savers and EnergyStar' 5, power designers of both the AC-DC and DC-DC power systems are working hard to meet the challenge if total increasing system level efficiency . With AC-DC system efficiencies typically average around a mere 65%, it is understandable that more weight has been placed on AC-DC since it is here that dramatic improvements can be made.
But as every percent saves energy, its now time to reexamine DC-DC systems to find creative ways to improve efficiency " across the entire load spectrum.
Focusing on a typical notebook personal computer, which is an extremely harsh yet common example as it converts based on a duty cycle of 6%. Typical peak efficiencies for a 46A, 2 phase Notebook VCORE solution with PWM controller and discrete MOSFET implementation are typically at 90% peak at current ratings of 10A per phase, reducing down to at 86% at full loads of 23A. This 10-13% loss in system efficiency is directly proportional to power and thermal dissipation.
Suffice it to say, all power system designers strive to minimize losses and heat. For these designs today, the complete notebook system is normally at 50-60W output and running at 85% efficiency " so that translates to a 9W power waste for every notebook PC in the form of heat and battery life.
The power MOSFET is the main culprit for power losses in these DC-DC circuits and by the adoption of advanced devices and careful optimization with their controller IC, this loss can be reduced. Thankfully there have been advances made in discrete MOSFET silicon. And innovative advanced thermal packaging technology has allowed power supplies to push the present limits of power density, efficiency and thermal performance.
However, these gains have not be achieved without tradeoffs. Higher power density is achieved but with a cost of increasing the overall power losses and higher temperatures on the silicon junction, the device case, and the overall PCB. Also, optimizing a DC/DC power supply for medium to peak currents comes at a sacrifice of efficiency in the light loads (such as standby or sleep mode), and visa versa. So, one must ask how these viable design options can converge and relate to overall improvements system efficiency?
By far the biggest - and as yet unachievable - challenge is to find a way to improve system efficiency at light, medium and heavy loads across the complete machine operating spectrum. Some would say the utopian power design.
At full loads, when our notebook PC is in start up mode or during a heavy processing sequence, the power system is dominated by conduction losses (I2R) of the low side MOSFET. Here we can select an ultra-high cell density low RDS(ON) FET housed in a dual-sided cooled package so that the losses will be significantly minimized.
As stated, most PCs spend a majority of their operating life in standby or sleep states. Therefore, it is essential that the power system must also allow for light load efficiency management where gate drive and switching losses are predominant at low output currents " say below 10A. Here driver impedance and MOSFETs have to be carefully optimized. A gate drive voltage level of 5V is preferred along with MOSFETs with ultra low gate charge.
In addition to this optimization, the driver IC will pulse skip switching cycles to minimize MOSFET switching loss and also now advanced PWM IC's can be equipped with a low-drive disable pin to effectively blank out the low side MOSFET completely allow for discontinuous conduction mode operation.
So by careful MOSFET selection, close optimization with the driver IC, light load pulse switching architectures and clever disable type functionality at ultra light loads, the design can start to move toward a higher level of overall system efficiency. Full load thermal design points can inch upward toward the 90% level, medium to light load levels can be touching 95% and ultra light loads don't immediately take a dive southward with such velocity. But while we progress and save a few watts of loss over today's designs, there is still some significant silicon research and development to be done before the utopian power curve can be seen.
|
