Sixteen-channel, 12-bit, 65 MSPS ADC incorporates data compression, port concentration to reduce I/O load

Santa Clara, Calif.—Designed to provide high-performance conversions while reducing corresponding digital-output bandwidth needs, the SAM1600 family of analog to digital converters (ADCs) from Samplify Systems, Inc.includes real-time data compression and port compression within the ICs. Using their patented Prism™ approach, the ADC output requires up to 75% less speed or LVDS I/O pairs, the vendor claims. The converters support multiple modes of operation: no compression, useful for basic test and evaluation; "bit-true" lossless compression, which provides full data integrity with some compression; and selectable lossy compression ratios, for trading bit-rate versus data fidelity, especially useful in applications which can tolerate some loss in exchange for greatly reduced traffic.

The 12-bit family (10.8 ENOB/68.5 dB SNR; no missing codes, guaranteed) consists, at present, of three ICs:

• SAM1600: 16 independent analog channels, 65 Msps, and port concentration to reduce LVDS pairs (can be configured as two independent octal ADCs, with separate frame and clock outputs, for legacy applications)
• SAM1605: 8 analog channels, 45/65 Msps, data compression and port concentration
• SAM1610: 16 analog channels, 45/65 Msps, data compression and port concentration

Note that the 16 independent channels of the SAM1600 and SAM1610 (thus no ADC front-end time-sharing) reduce crosstalk below the ADC's noise floor.

Figure 1: Block diagram of Samplify Systems' SAM1610 ADC with integral compression.
(Click on image to enlarge)

For compatibly with legacy ADCs, the converters provide one serialized LVDS output at speeds up to 800 Msps per channel. However, by using data compression and port concentration, and with dissipation of 50 milliwatts per channel, the vendors claims users can significantly reduce power consumption as well as I/O pins between the ADC and FPGA; for example, Samplify says that for a 256-channel ultrasound system a 75% reduction ion LVDS pairs translates to 384 fewer FPGA pins and board traces. The compression algorithm also features low latency and can work with packet sizes of just 96 samples.

Typical specifications with a 50 MHz clock include differential nonlinearity of ±0.9 LSB; integral nonlinearity of ±1.0 LSB; differential input voltage range of 1.4 V_pp; and SINAD of 67 dB; worst-case crosstalk is -75 dBFS. Two-tone distortion is -75 dBFS (one analog input at 10 MHz at -0.5 dBFS and another at 10.1 MHz at -20.5 dBFS).

The converters include an internal voltage reference and PLL-based clocking circuitry, and use an SPI interface for setup and control. All members of the family are housed in a 12 x 12 mm BGA package. Customers also receive a royalty-free license for the company's decompression FPGA IP or software. An ADC evaluation board is also offered, at $1995.—Bill Schweber

Price and availability: Prices range from $39.50 (SAM1605) to $79.00 (SAM1610) each, in 1000-piece orders; parts are available now.

For more information: Samplify Systems, Inc., www.samplify.com, 888-LESS-BITS.